1. Field of the Invention
The present invention relates to a thin film transistor array panel, and more particularly, to a thin film transistor array panel that can improve the response time of a liquid crystal display.
2. Description of the Related Art
Liquid crystal displays (LCDs) generally include an upper panel, a lower panel and a liquid crystal material having a dielectric anisotropy injected between the upper panel and the lower panel. Light transmission through the panels is controlled by varying the strengths of the electric fields applied to the upper and lower panels, thereby controlling an orientation of the liquid crystal material and displaying a desired image.
In recent years, a variety of studies have been conducted with the goal of discovering how to increase the response time or speed of a liquid crystal display. Several solutions have been proposed to increase the response speed of liquid crystal, including improvement of driving conditions, changing liquid crystal materials, and changing liquid crystal cell modes. Specifically, the response time may be improved by optimizing a driving voltage, often denoted as an analog source voltage (AVDD), to increase the rise time. However, a consequence of this may be that power dissipation may also increase. Other solutions have been tried including reducing an offset voltage, which shortens the fall time, thereby improving the response speed of the liquid crystal to some extent. However, it is quite difficult to reduce the offset voltage to a level that is equal to or less than a predetermined level while maintaining a gamma value adjustment within the target gamma curve. Improvement of the response speed of liquid crystal can also be achieved in part through optimization of a common voltage, which may introduce several other problems such as residual images, flickering, or the like. Limitations associated with developing alternative materials have been a barrier to changing to a different liquid crystal material.
Meanwhile, the voltage V typically applied to the liquid crystals for a time period corresponding to one frame may be expressed by the following formula:V=Q/(Cst+Clc)where the liquid crystal capacitance Clc is changed in the one frame due to an anisotropic dielectric constant while the amount Q of electric charge applied to the liquid crystals is constant based on the electric charge conservation law, so that the data voltage V applied to the liquid crystals is changed. That is to say, as the liquid crystal capacitance Clc is changed, the data voltage V applied to the pixel electrode is reduced, so that a cusp, or void, may occur. As a result, the response time becomes longer.
For example, it is assumed that a black state refers to a state in which the data voltage (4 V) is applied to the pixel electrode, a white state refers to a state in which the data voltage (0.5 V) is not applied to the pixel electrode, a value of the storage capacitor Cst is 0 when the pixel electrode is changed from the black state to the white state, a dielectric constant is 13.5 when the pixel electrode is in the black state, and a dielectric constant is 3.6 when the pixel electrode is in the white state. Based on the above assumptions, when the pixel electrode is in the black state, the amount Q of electric charge applied to the liquid crystals is 6.75, as calculated by the formula: Q=(Cst+Clc)*V. Since the amount Q of electric charge applied to the liquid crystals is maintained based on the electric charge conservation law, when the pixel electrode is in the white state, the voltage V applied to the liquid crystals is 1.875 V, as calculated by the formula {6.75=(0+3.6)*V}. Therefore, when the data voltage is not applied to the pixel electrode, the data voltage V that was applied to the pixel electrode is changed. In this case, the data voltage V is not 0.5 V but 1.875 V, that is, a gray state, suggesting formation or occurrence of a cusp. The cusp occurs at a boundary between the current frame and the next frame due to insufficient capacitance of the storage capacitor Cst.